The base board

Augur One

Everything your firmware expects to find around it: sensors that answer, loads that push back, buses that respond, and faults that arrive when the agent decides they should.

The rig you would have built by hand

A sensor breakout on a jumper harness, a motor with a load on it, a bench supply, a logic analyzer, and a person to power-cycle the whole thing when the DUT locks up.

Augur One is that bench as one board. Your DUT board plugs in, and the world your firmware reads is generated in hardware and driven from the network.

CAD render of the Augur One assembly: Ethernet and USB-C at the left edge, the FPGA and real-time MCU across the middle, ten analog module slots populated with green modules, and the DUT connectors along the far edge.
CAD render · in fabrication
210 x 130 mmone base board
One Cat-6power and network
up to 216 I/O + 40 analogto the DUT

Will your chip fit

Your DUT board carries the part under test and whatever it needs to boot. The connectors bring it everything else.

up to 216digital I/O across 4 adjustable 1.2–3.3 V banks. Any pin can be SPI, I2C, UART, CAN, PWM or an encoder channel.
+ up to 40analog channels on top of those, in 10 slots of 4, high-speed or low-speed
1.8–5 VDUT supply
Dual-rangecurrent sense: 250 µA/LSB on the run range, 31 nA/LSB on the sleep range
SWD or JTAGonto any I/O pin. No fixed debug pinout to design around.
2x Ethernetplus 2x USB OTG and a Wi-Fi/BLE peer, all reaching the DUT
We meet your board at the controller boundary. Your power stage stays off the bench, and your firmware still sees the signals it would see in the product.

Where each job runs

Emulating a world is two kinds of work, and they want different silicon.

Sensor register models, bus slaves, PWM and encoder decode, fault injection, capture Lattice ECP5 FPGA Timing is decided in gateware, so the DUT's bus is answered at the DUT's clock
Plant models, closed-loop state, physics integration STM32N657, Cortex-M55 State advances between the DUT's samples
The agent, test authoring, verdicts, evidence Your bench computer None of it is real-time, so none of it can stall the plant

The first two rows are Augur One. The third is a Linux machine with gigabit Ethernet that you supply: we do not sell it, and a lab that already has machines does not buy another one.

One cable

Power over Ethernet is standard, 802.3bt Type 4: one run of Cat-6 carries power and network, so a bench is a switch port. USB-C is the backup link, the recovery path, and an alternative power input when there is no PoE switch on hand.

One engineer, as many benches as features.

It comes back without you

A dedicated supervisor MCU, an STM32H563, sits on its own rail and owns recovery and DUT power. The board is built around one rule: Ethernet must not drop while something is being recovered.

DUT wedged
supervisor cuts and restores DUT power: the exact case you used to walk over for
Real-time MCU wedged
supervisor asserts its reset line
FPGA misconfigured
supervisor pulses PROGRAMN and the FPGA reloads from NOR
Bitstream corrupt
supervisor owns the FPGA's JTAG: it SRAM-loads a known-good image or reprograms the config flash
Switch hangs
the one case that drops the link: the supervisor resets the switch and the host reconnects

Watch an agent run a task on the bench.

Neither the FPGA nor the real-time MCU has a power switch anywhere on the board, so half-powered states do not exist to get stuck in. That comes from the schematic, not from firmware discipline.

Where your source goes

Nowhere. The agent runs on the bench computer you supply, inside your network, and your firmware source stays on it. What leaves is the run record: verdicts, captures, and the commit hash each iteration ran against.

What runs today

Closed loop on real silicon
running today on Oracova development hardware: BLDC plant and hall encoder against an STM32F411
Fault library
running: hall faults scored FAIL on the unguarded build, PASS with the guard patch
Unmodified Betaflight
running: on real silicon, closing its 8 kHz loop against the world in FPGA fabric
Augur One
in fabrication, first article pending. Everything above runs today on development hardware; Augur One puts it on one board.

Bring your board to the bench.

See the full specification Price your bench Book 15 minutes